High data rate multilevel clock recovery system
US9712347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Dec 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/03
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.