Topology configuration of processing elements array by using packets
US9712396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/0803
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In some aspects, the disclosure is directed to methods and systems for topology configuration of an array of packet processing elements via a topology configuration packet. Each processing element may include input packet busses from a first plurality of neighboring processing elements and output packet busses to a second plurality of neighboring processing elements. Each processing element may receive the configuration packet from one of the first plurality of neighboring elements, set its own topology configuration register according to predetermined values within the packet, and forward the packet out all of its outputs, in the same manner as a standard packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.