Run-time parallelization of code execution based on an approximate register-access specification
US9715390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2015 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | May 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.