Memory control apparatus
US9715427B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2012 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Jan 26, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal buffer caches data from a memory. A memory address conversion unit receives as input a read request from a request source. A hit determination unit determines whether or not data of any one of two or more read out candidate addresses in which payload data requested by the read request and corresponding are stored has been cached or is going to be cached in the internal buffer. When data of any one of the addresses has been cached or is going to be cached in the internal buffer, a command issue interval control unit outputs to the memory a partial read command to instruct to read data from an address other than the address of the data that has been cached or is going to be cached in the internal buffer out of the read out candidate addresses, after a predetermined delay time has elapsed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.