System and method for cache data recovery
US9715428B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2014 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Oct 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a first host device, a second host device, and first and second cache controllers. A cache controller includes a cache memory interface, a first peripheral interface that communicates with the first host device, a second peripheral interface that communicates with the second host device, logic circuitry that loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands, and error checking circuitry that detects an uncorrectable error in a first cache controller/memory pair and indicates the uncorrectable error condition to at least one of the first and second host devices. At least one of the first host device or the second host device writes contents of the cache memory of the second cache controller/memory pair to a main memory in response to the indication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.