Cache memory control circuit and processor
US9715461B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2014 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a cache memory control circuit includes: a hit determination section; a refill processing section; a search section configured to determine a refill candidate way by searching for the way candidate for a refill process from a plurality of ways based on an LRU algorithm when the hit determination section detects a cache miss; a binary tree information section configured to store binary tree information for the LRU algorithm; a conflict detection section; and a control section. The control section updates the binary tree information in the binary tree information section by using way information of the way where the refill process is being executed when the conflict detection section determines that the way where the refill process is being executed and the refill candidate way match each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.