Computer implemented system and method of translation of verification commands of an electronic design
US9715566B2 · kind B2 · utility
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31Claims
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Key dates
| Filing date | May 8, 2015 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Aug 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.