Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems
US9715655B2 · kind B2 · utility
14Cited by
7References
28Claims
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Key dates
| Filing date | Jul 10, 2014 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems. Invention provides iterative training of memristor crossbar arrays for neural networks by applying voltages corresponding to selected training patterns. Error is detected and measured as a function of the actual response to the training patterns versus the expected response to the training pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.