Optimal data eye for improved Vref margin
US9715907B1 · kind B1 · utility
2Cited by
2References
10Claims
0Family size
Assignee
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Key dates
| Filing date | May 9, 2016 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | May 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.