Single port SRAM memory cell driven by two word lines in asynchronous manner and memory employing the same
US9715922B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory comprised of a plurality of single port SRAM memory cells, each driven by two word lines in an asynchronous manner has a hold mode, a read mode and a write mode. Each of the single port SRAM memory cells includes a first write switch, a second write switch and a latch. The first write switch is electrically connected to a first word line and is turned on by a first turn-on signal transmitted by the first word line. The second write switch is electrically connected to a second word line and is turned on by a second turn-on signal transmitted by the second word line. When the memory is in the write mode, the second write switch is turned on by the second turn-on signal having a delay with respect to the first turn-on signal, thereby blocking the pseudo read of the unselected memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.