Gate aligned contact and method to fabricate same
US9716037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Jan 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.