Manufacturing method of dual gate TFT substrate and structure thereof
US9716119B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 2015 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Oct 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
Disclosed are a manufacturing method of a dual gate TFT substrate and a structure thereof. The manufacturing method of a dual gate TFT substrate includes sequentially manufacturing a bottom gate, a first isolation layer, an island shaped semiconductor layer, and a second isolation layer on a substrate; then, depositing a second metal layer, and implementing a patterning process to the second metal layer with one mask to form a source, a drain and a top gate at the same time; and then, sequentially manufacturing a third isolation layer and a pixel electrode. It can promote the stability of the TFT, reduce the amount of the masks, and shorten the process flow, simplifying the manufacture process and diminishing the production cost. In the structure of the dual gate TFT substrate, the structure is simple, and the stability of the TFT is better, and easy to manufacture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.