Bias control for stacked transistor configuration
US9716477B2 · kind B2 · utility
33Cited by
35References
66Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2015 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Feb 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.