Transistor switch with back-gate biasing
US9716500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2015 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Aug 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Driving a back-gate of a transistor with a follower signal that corresponds to an information signal. At least some of the illustrative embodiments are methods including: passing an information signal from a drain terminal to a source terminal of a main field effect transistor (FET), the information signal has a peak-to-peak voltage; generating a follower signal that corresponds to the information signal, the follower signal electrically isolated from the information signal, and the follower signal has a peak-to-peak voltage lower than the peak-to-peak voltage of the information signal; and applying the follower signal to a back-gate of the main FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.