DLL calibration method for fast frequency change without re-locking
US9716507B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2016 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Apr 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency without the need to relock the DLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.