Patent · US Active

Using thresholds to gate timing packet generation in a tracing system

US9716646B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Tsvika Kurts · Haifa, IL
Beeman C. Strong · Portland, US
Ofer Levy · Atlit, IL
Gabi Malka · Haifa, IL
Zeev Sperber · Jerusalem, IL

Key dates

Filing date	Jul 17, 2014
Grant date	Jul 25, 2017
Priority date	—
Expiry date	Jul 28, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH04L43/106
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.