Radiation hardened chip level integrated recovery apparatus, methods, and integrated circuits
US9720026B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2016 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Aug 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/001
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and integrated circuits that provide radiation hardening through chip level integrated recovery are provided. The apparatus may include first and second circuits within a partition of an integrated circuit having isolated grounds and a state machine configured to monitor current leakage of the first circuit while the first circuit is powered on and to power on the second circuit and power off the first circuit when the monitored first circuit current leakage exceeds a first current leakage threshold. The method may include powering a first circuit of a partition within an integrated circuit, monitoring current leakage of the first circuit while the first circuit is powered on and the second circuit is powered off, storing values representing a current leakage signature over an operating range of the first circuit, and powering off the first circuit and powering on the second circuit when the monitored first circuit current leakage exceeds a corresponding first current leakage threshold with the stored values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.