Method and system for printed circuit board layout
US9721053B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 23, 2016 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Apr 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0296
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system for printed circuit board layout includes a processing unit and a memory unit. The memory unit stores physical node data and virtual node data. The processing unit is electrically coupled to the memory unit and configured to execute steps of a method for printed circuit board layout. In particular, the physical node data of a printed circuit board (PCB) is acquired. The physical node data include a plurality of data structure and coordinate points of the physical nodes. The virtual node data of the PCB is acquired. The virtual node data include a plurality of data structure of the virtual nodes. A corresponding relation of the physical nodes and the virtual nodes is determined according to the physical node data and the virtual node data. The virtual nodes are disposed at the physical node coordinate points according to the corresponding relation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.