Wafer bonding method and device with reduced thermal expansion
US9721824B2 · kind B2 · utility
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12References
13Claims
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Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.