TFT, array substrate and method of forming the same
US9722094B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 9, 2015 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Jan 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6745
Abstract
The present invention proposes a TFT, an array substrate, and a method of forming a TFT. The TFT includes a substrate, a buffer layer, a patterned poly-si layer, an isolation layer, a gate layer, and a source/drain pattern layer. The poly-si layer includes a heavily doped source and a heavily doped drain, and a channel. The gate layer includes a first gate area and a second gate area. The source/drain pattern layer includes a source pattern, a drain pattern and a bridge pattern, with the source pattern electrically connecting the heavily doped source, the drain pattern electrically connecting the heavily doped drain, and one end of the bridge pattern connecting the first gate area and the second gate area. The driving ability of the present inventive TFT is enhanced without affecting the leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.