Semiconductor device comprising successive approximation register analog to digital converter with variable sampling capacitor
US9722624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2016 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Mar 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and operating method thereof are provided. The semiconductor device includes a mode controller configured to output a control signal of a first level in a first mode, and output a control signal of a second level that is different from the first level in a second mode that is different from the first mode; and a successive approximation register analog-to-digital converter (SAR ADC) configured to convert an analog input signal into a digital output signal using a plurality of variable sampling capacitors, wherein each of the plurality of variable sampling capacitors comprises a first sampling capacitor having a first capacitance, and a second sampling capacitor having a second capacitance, wherein, in the first mode, the SAR ADC is configured to receive the control signal of the first level and connect the first sampling capacitor and the second sampling capacitor to either of a first voltage and a second voltage that is different from the first voltage to convert the analog input signal into the digital output signal, and wherein, in the second mode, the SAR ADC is configured to receive the control signal of the second level and connect any one of the first …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.