Clock domain bridge static timing analysis
US9722767B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2015 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Jun 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Examples for performing static timing analysis on clocked circuits are described. An example static timing analysis computing device includes a logic device, and a storage device holding instructions executable by the logic device, the instructions including instructions executable to receive an input representative of one or more delays within a signal path in a cross-domain circuit, the cross-domain circuit configured to transfer data between a first domain having a first clock and a second domain having a second clock asynchronous with the first clock, receive an input representative of a static timing analysis constraint to be met by a signal traveling the signal path in the cross-domain circuit, apply the constraint in a static timing analysis of the signal path in the cross-domain circuit, and output a result based upon applying the static timing analysis constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.