Methods for early write termination with non-volatile memory
US9727112B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2014 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Dec 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.