Data storage device and flash memory control method
US9727271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2017 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Feb 21, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.