Virtual machine function based sub-page base address register access for peripheral component interconnect device assignment
US9727359B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Jan 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A value stored in a guest device register is received from a virtual machine. A hypervisor generates a page table including a first mapping between the value stored in the guest device register and a first address of the host operating system and a second mapping between a second address of the guest operating system and a third address of a virtual machine function on the host operating system. The hypervisor modifies a first access status of the first mapping to include rendering memory of the host device referenced by the value stored in the guest device register accessible to the virtual machine function, and a second access status of the second mapping to include rendering the virtual machine function accessible to the virtual machine. The hypervisor initializes code on the virtual machine function to access the memory of the host device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.