Patent · US Active

Memory error detection system

US9727408B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Aarul Jain · New Delhi, IN
Dirk Wendel · Unterhaching, DE

Key dates

Filing date	Dec 20, 2015
Grant date	Aug 8, 2017
Priority date	—
Expiry date	Apr 19, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/167
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.