Configuration structure and method of a block memory
US9727415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2014 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Nov 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.