Semiconductor devices with improved source/drain contact resistance and methods of manufacturing the same
US9728465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Oct 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0193
Abstract
In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer. A second heat treatment process is performed such that the substrate and the second metal layer react with each other to form a third metal-semiconductor composite pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.