Enhanced flash chip and method for packaging chip
US9728520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2013 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.