Variable clock phase generation method and system
US9729157B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Feb 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.