Array substrate, liquid crystal display panel and display device
US9733535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2012 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Nov 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/134363
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate comprises: a substrate; and a plurality of gate lines (101) and a plurality of data lines (102), which are formed on the substrate. Two adjacent gate lines (101) and two adjacent data lines (102) intersect with each other to form a pixel region. Each pixel region comprises two pixel electrodes (103) and two thin-film transistors (TFTs). The drain electrodes of two thin-film transistors (TFTs) are respectively connected to two pixel electrodes (103), the source electrodes of two thin-film transistors (TFTs) are respectively connected to two data lines, and the gate electrodes of two thin-film transistors (TFTs) are connected to one of two gate lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.