Dynamic low power states characterization
US9733696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Feb 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.