Systems and methods for individually configuring dynamic random access memories sharing a common command access bus
US9734878B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Apr 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.