Patent · US Active

Circuits and methods for performance optimization of SRAM memory

US9734896B2 · kind B2 · utility

2Cited by

9References

14Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Per Torstein Roine · Oslo, NO
Vinod Menezes · Bengaluru, IN
Mahesh M. Mehendale · Bengaluru, IN
Vamsi Gullapalli · Savanuru, IN
Premkumar Seetharaman · Bengaluru, IN

Key dates

Filing date	Jun 30, 2016
Grant date	Aug 15, 2017
Priority date	—
Expiry date	Jun 30, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.