Patent · US Active

Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories

US9734920B2 · kind B2 · utility

1Cited by

7References

17Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Kevin W. Gorman · Saint Johnsbury Center, US
Michael R. Ouellette · Colchester, US
Patrick E. Perry · South Burlington, US

Key dates

Filing date	Sep 28, 2015
Grant date	Aug 15, 2017
Priority date	—
Expiry date	Sep 28, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/3602
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.