Memory device
US9735014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2015 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Apr 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.