Method for forming semiconductor device structure with fine line pitch and fine end-to-end space
US9735028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2015 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Jul 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.