Seal ring structure to avoid delamination defect
US9735116B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | May 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/585
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate, a plurality of integrated circuit devices on the semiconductor substrate, and a seal ring structure surrounding each one of the integrated circuit devices. The seal ring structure includes a plurality of interlayer dielectric layers and a plurality of hollow through-hole structures disposed within each of the interlayer dielectric layers. Each of the hollow through-hole structure within an interlayer dielectric layer includes a through-hole disposed within one of the interlayer dielectric layers, a diffusion barrier layer formed at the bottom, sidewalls and the top of the through-hole, and a seed layer disposed on the diffusion barrier layer. The diffusion barrier layer and the seed layer cover the top of the through-hole so that the through-hole has a void to form the hollow through-hole structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.