Array substrate, display device, and method for manufacturing the array substrate
US9735182B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 7, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Dec 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6745
Abstract
An array substrate includes a substrate and data lines and scan lines arranged on the substrate. The data lines and the scan lines define plural pixel regions. A thin film transistor is arranged in each pixel region and includes a gate electrode, a source electrode, a drain electrode, and an active region. The gate electrode is arranged above the active region. The source electrode and the drain electrode are arranged at two opposite sides of the active region respectively. A light shielding metal layer is further arranged in each pixel region. The light shielding metal layer and the data lines are arranged in the same layer on the substrate. The light shielding metal layer is arranged under the active region and at least partially overlaps with the active region. The data line is close to the source electrode and does not overlap with the active region at least partially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.