Cascaded multi-level power converter
US9735664B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2014 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Jan 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/0095
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multi-level power converter comprising: n input stages (Ein_n), n being at least equal to 1, each input stage comprising n+1 identical input converters (CONVx_En) connected together, the input converters (CONVx_En) exhibiting an identical topology, chosen from among the architectures of the NPC (Neutral Point Clamped), ANPC (Active Neutral Point Clamped), NPP (Neutral Point Piloted) and SMC (Stacked Multicell Converter); an output stage (Eout) connected to the input stage of rank 1 and comprising an output converter (CONVs) supplied with a differential voltage (Vfloat) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, the output converter (CONVs) exhibiting a topology chosen from among an architecture with floating capacitor (FC), SMC (Stacked Multicell Converter), NPC (Neutral Point Clamped), NPP (Neutral Point Piloted) and ANPC (Active Neutral Point Clamped).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.