Digital measurement of DAC timing mismatch error
US9735797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Nov 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/412
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.