Coherent transceiver architecture
US9735881B1 · kind B1 · utility
Assignee
Inventors
- Oscar E. Agazzi
- Diego Ernesto Crivelli
- Paul Voois
- Ramiro Rogelio Lopez
- Jorge Manuel Finochietto
- Norman L. Swenson
- Mario Rafael Hueda
- Hugo Santiago Carrer
- Vadim Gutnik
- Adrián Ulises Morales
- Martin Ignacio Del Barco
- Martin Carlos Asinari
- Federico Nicolas Paredes
- Alfredo Javier Taddei
- Mauro Marcelo Bruni
- Damian Alfonso Morero
- Facundo Abel Alcides Ramos
- María Laura Ferster
- Elvio Adrian Serrano
- Pablo Gustavo Quiroga
- Roman Antonio Arenas
- Matias German Schnidrig
- Alejandro Javier Schwoykoski
Key dates
| Filing date | May 6, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0075
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.