Method for storing and retrieving packets in high bandwidth and low latency packet processing devices
US9736069B1 · kind B1 · utility
2Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Jun 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.