Scan chain for memory sequential test
US9739833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N−1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N−1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.