Patent · US Active

On-chip clock controller

US9740234B1 · kind B1 · utility

2Cited by

6References

27Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Hong Sun Kim · Seoul, KR
Paul F. Policke · Cedar Park, US
Anirudh Kadiyala · Austin, US

Key dates

Filing date	Mar 31, 2016
Grant date	Aug 22, 2017
Priority date	—
Expiry date	Mar 31, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/284
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An on-chip clock controller includes a primary clock gating cell and a secondary clock gating cell. The primary clock gating cell includes a first clock input terminal coupled to receive an input clock signal and a first enable input terminal coupled to receive an enable signal. The primary clock gating cell also include a first clock output terminal configured to generate a first output clock signal based at least in part on the input clock signal and the enable signal. The secondary clock gating includes a second clock input terminal coupled to receive the input clock signal and a second clock output terminal configured to generate a second output clock signal based at least in part on the input clock signal. The enable signal is based at least in part on the second output clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.