Drive array policy control
US9740426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2014 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Nov 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus can include an interface; cache memory; a plurality of drives; and a controller that includes detection circuitry, a write through mode and a write back mode, where the write through mode writes information received via the interface to the plurality of drives, where the write back mode writes information received via the interface to the cache memory and writes information written to the cache memory to the plurality of drives, and where the detection circuitry selects the write through mode based at least in part on detection of a first condition and selects the write back mode based at least in part on detection of a second condition, where the first condition and the second condition differ.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.