Method and apparatus for asynchronous processor removal of meta-stability
US9740487B2 · kind B2 · utility
3Cited by
22References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Feb 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/3883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.