Implementing out of order processor instruction issue queue
US9740495B2 · kind B2 · utility
5Cited by
7References
8Claims
0Family size
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Key dates
| Filing date | Feb 20, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Oct 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.