Processor with memory-embedded pipeline for table-driven computation
US9740496B2 · kind B2 · utility
1Cited by
4References
13Claims
0Family size
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Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | May 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.