Static random access memory with reduced write power
US9741430B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Oct 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.